Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
FPGA Implementation of MIL-STD-1553B Bus Protocol

FPGA Implementation of MIL-STD-1553B Bus Protocol

Yousaf, Jawad
Mehmood, Iftekhar

Paperback

Technology & Engineering

ISBN10: 3659384194
ISBN13: 9783659384196
Publisher: Lap Lambert Academic Pub
Published: Jun 13 2013
Pages: 156
Weight: 0.52
Height: 0.36 Width: 6.00 Depth: 9.00
Language: English
Modern day avionics and satellite communication systems communicate with each other using MIL-STD- 1553B bus protocol. This book aim to provide an intensive study for the software and hardware level implementation of MIL-STD-1553B bus protocol on FPGA board using a new methodology of digital phase lock loop (DPLL). The book describes the basics of bus protocol, modular level implementation of different units of protocol and software & hardware implementation issues and their solutions. ISE Xilinx Spartan 3 FPGA kit is used for the execution of different modules of protocol like UART, Bus Controller, Manchester encoder/decoder and DPLL. DPLL is used for data clock recovery from encoded Manchester data of the channel at receiver end, instead of implementing common practice of initiating a separate clock for encoded Manchester data processing. Usage of DPLL, resolves the synchronization issues, a major concern in high data rate embedded systems and increases the integrity and reliability of the system. The actual implementation of different transactions of bus i.e. BC to RT and RT to RT is discussed in detailed.

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