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Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Design Methodology for RF CMOS Phase Locked Loops

Design Methodology for RF CMOS Phase Locked Loops

Hardcover

Technology & Engineering

Currently unavailable to order

ISBN10: 1596933836
ISBN13: 9781596933835
Publisher: Artech House Inc
Published: Feb 1 2009
Pages: 226
Weight: 1.01
Height: 0.67 Width: 6.30 Depth: 9.33
Language: English
Engineers face stiff challenges in designing phase-locked loop (PLL) circuits for wireless communications thanks to phase noise and other obstacles. This practical book comes to the rescue with a proven PLL design and optimization methodology that lets designers assess their options, predict PLL behavior, and develop cost-effective PLLs that meet performance requirements no matter what IC (integrated circuit) challenges they come up against. This uniquely comprehensive toolkit takes designers step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and Cmos realizations for each PLL building block. It provides a sample design of a fully integrated PLL for Wlan applications, demonstrating every step from specs definition and circuit characterization to layout generation and circuit schematics.

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