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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
VLSI Architecture of Block Coder in JPEG 2000

VLSI Architecture of Block Coder in JPEG 2000

Sarawadekar, Kishor

Paperback

Technology & Engineering

Currently unavailable to order

ISBN10: 3843355843
ISBN13: 9783843355841
Publisher: Lap Lambert Academic Pub
Published: Nov 15 2010
Pages: 76
Weight: 0.27
Height: 0.18 Width: 6.00 Depth: 9.00
Language: English
With the growth in multimedia technology, demand for high speed real time image compression system has also increased. JPEG 2000 still image compression standard is developed to cater such application requirements. It offers numerous advantages over traditional JPEG standard. The key algorithms adopted in this standard are discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). Both the algorithms are computation intensive and when implemented on general purpose processor, they are unsuitable for real time applications. Therefore, to meet the timing constraints imposed by the real time systems dedicated VLSI implementation of these algorithms is imperative. EBCOT is a two-tier coder. Tier-1 is a context based adaptive arithmetic coder and Tier-2 performs layered bit stream formation. Tier-1 is further partitioned into block coder and MQ coder. To a novice, it is difficult to grasp the operating principle of the block coder and hence it is difficult to realize high speed JPEG 2000 architecture. The author has made an attempt to demystify these concepts and presented a simplified VLSI architecture of the block coder in this book.

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