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Time-Interleaved Analog-To-Digital Converters
Paperback
Series: Analog Circuits and Signal Processing
ISBN13: 9789400799516
Publisher: Springer Nature
Published: Dec 13 2014
Pages: 136
Weight: 0.50
Height: 0.33 Width: 6.14 Depth: 9.21
Language: English
Preface.
1 Introduction. 1.1 Analog-to-digital conversion. 1.2 Architecture. 1.3 Outline.
2 Time-interleaved Track and Holds. 2.1 Introduction. 2.2 Mismatch between channels. 2.3 Time-interleaved Track and Hold architectures. 2.4 Track and Hold buffers. 2.5 Bottom-plate sampling in a time-interleaved ADC. 2.6 Number of channels. 2.7 Calibration. 2.8 Jitter requirement on the sample-clock. 2.9 Summary and conclusions.
3 Sub-ADC architectures for time-interleaved ADCs. 3.1 Introduction. 3.2 The Successive Approximation ADC. 3.3 Efficiency of SA-ADC versus pipeline ADC. 3.4 Summary and conclusions.
4 Implementation of a high-speed time-interleaved ADC. 4.1 Introduction. 4.2 Clock generation. 4.3 Track and Hold. 4.4 Sub-ADC. 4.5 Calibration. 4.6 Layout. 4.7 Measurements. 4.8 Improved design. 4.9 Conclusions.
5 Summary and conclusions. 5.1 Summary. 5.2 Conclusions. 5.3 Original contributions. 5.4 Recommendations for future research.
About the author. Bibliography. Index. List of Symbols. List of Abbreviations.
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