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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Synthesizable VHDL Design for FPGAs

Synthesizable VHDL Design for FPGAs

Bezerra, Eduardo Augusto
Lettnin, Djones Vinicius

Hardcover

Technology & EngineeringProgramming

ISBN10: 3319025465
ISBN13: 9783319025469
Publisher: Springer Nature
Published: Oct 31 2013
Pages: 157
Weight: 0.91
Height: 0.44 Width: 6.14 Depth: 9.21
Language: English

The methodology described in this book is the result of many years of research experience in the field of synthesizable VHDL design targeting FPGA based platforms. VHDL was first conceived as a documentation language for ASIC designs. Afterwards, the language was used for the behavioral simulation of ASICs, and also as a design input for synthesis tools. VHDL is a rich language, but just a small subset of it can be used to write synthesizable code, from which a physical circuit can be obtained. Usually VHDL books describe both, synthesis and simulation aspects of the language, but in this book the reader is conducted just through the features acceptable by synthesis tools. The book introduces the subjects in a gradual and concise way, providing just enough information for the reader to develop their synthesizable digital systems in VHDL. The examples in the book were planned targeting an FPGA platform widely used around the world.

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