Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
State Machines in VHDL Multipliers Vol. 2: State Machine Design for Arithmetic Processes

State Machines in VHDL Multipliers Vol. 2: State Machine Design for Arithmetic Processes

Hawkins, Daryl Ray

Paperback

Series: State Machines in VHDL, Book 2

Technology & Engineering

ISBN10: 1493690531
ISBN13: 9781493690534
Publisher: Createspace
Published: Dec 18 2013
Pages: 72
Weight: 0.24
Height: 0.15 Width: 5.98 Depth: 9.02
Language: English
This booklet contains all the information required to implement multiplier circuits in FPGA and ASIC devices as state machines. Four designs are provided ranging from simple to high performance with suggestions for even higher performance. Also included is a comprehensive chapter on normalizing and rounding, fixed-point as well as floating-point. The use of carry-save adders for partial product multiplication. Combining embedded array multipliers available in most FPGA devices for fashioning high perform large operand multipliers. Each design covered has a fully coded and fully functional design in VHDL as a state machine, with normalizing, rounding, and overflow included. Each design is also scalable in terms of operand size and the size of integer and fractional portions.

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