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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling

Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling

Mandal, Ayan
Khatri, Sunil P.
Mahapatra, Rabi

Hardcover

Technology & EngineeringGeneral Computers

ISBN10: 1461494044
ISBN13: 9781461494041
Publisher: Springer Nature
Published: Nov 14 2013
Pages: 143
Weight: 0.75
Height: 0.60 Width: 6.00 Depth: 9.00
Language: English
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

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