Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
612-822-4611

  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Real Chip Design and Verification Using Verilog and VHDL

Real Chip Design and Verification Using Verilog and VHDL

Cohen, Ben

Paperback

Technology & EngineeringGeneral Computers

ISBN10: 1539769712
ISBN13: 9781539769712
Publisher: Createspace Independent Publishing Platform
Published: Oct 6 2002
Pages: 426
Weight: 2.16
Height: 0.87 Width: 8.50 Depth: 11.00
Language: English
Real Chip Design and Verification Using Verilog and VHDL addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices, and uses Verilog and VHDL as a tool for expression of the desired architectures. This book is not intended to teach either HDL, as there are several books specifically geared toward teaching the languages. However, it provides various architectural design primitives, applications, and verification techniques, along with design methodologies and common practices.

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