Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
612-822-4611

  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Low-Power High-Speed Adcs for Nanometer CMOS Integration

Low-Power High-Speed Adcs for Nanometer CMOS Integration

Cao, Zhiheng
Yan, Shouli

Hardcover

Series: Analog Circuits and Signal Processing

Business GeneralTechnology & Engineering

ISBN10: 1402084498
ISBN13: 9781402084492
Publisher: Springer
Published: Jul 8 2008
Pages: 95
Weight: 0.74
Height: 0.31 Width: 6.14 Depth: 9.21
Language: English

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested.

1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.

1 different editions

Also available

Also in

Technology & Engineering

View All