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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Low-Power 8-Bit Pipelined Adc with Current Mode Mdac

Low-Power 8-Bit Pipelined Adc with Current Mode Mdac

Shahzad, Khurram

Paperback

Technology & Engineering

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ISBN10: 3843370265
ISBN13: 9783843370264
Publisher: Lap Lambert Academic Pub
Published: Nov 3 2010
Pages: 76
Weight: 0.27
Height: 0.18 Width: 6.00 Depth: 9.00
Language: English
In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying digital-to-analog converter (MDAC). The main focus is to design and optimize the MDAC. We design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages consisting of Sample-and-Hold, 1.5-bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2-bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in Verilog-A and MATLAB. A first order digital error-correction algorithm is implemented in MATLAB. The design is simulated in UMC 0.18μm technology in Cadence environment.

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