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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Low-Power Variation-Tolerant Design in Nanometer Silicon

Low-Power Variation-Tolerant Design in Nanometer Silicon

Bhunia, Swarup
Mukhopadhyay, Saibal

Paperback

Technology & EngineeringGeneral Computers

ISBN10: 1489981578
ISBN13: 9781489981578
Publisher: Springer Nature
Published: Oct 10 2014
Pages: 440
Weight: 1.40
Height: 0.93 Width: 6.14 Depth: 9.21
Language: English
Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.

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