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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms

Hachtel, Gary D.
Somenzi, Fabio

Paperback

Technology & EngineeringGeneral Computers

ISBN10: 1475770367
ISBN13: 9781475770360
Publisher: Springer Nature
Published: Mar 18 2013
Pages: 564
Weight: 2.26
Height: 1.21 Width: 7.00 Depth: 10.00
Language: English
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

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