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Implementation of a Binary Floating Point Fused Multiply-Add Unit

Implementation of a Binary Floating Point Fused Multiply-Add Unit

Paperback

Technology & Engineering

ISBN10: 3846546216
ISBN13: 9783846546215
Publisher: Lap Lambert Academic Pub
Published: Dec 16 2012
Pages: 104
Weight: 0.36
Height: 0.25 Width: 6.00 Depth: 9.00
Language: English
The fused multiply add (FMA) operation is very important in many scientific and engineering applications. It is a key feature of the floating-point unit (FPU), which greatly increases the floating-point performance and accuracy.Many approaches are developed on floating-point fused multiply add unit to decrease its latency.two of these approaches are implemented in the Verilog hardware description language. ModelSim10.0c is a used to compile Verilog codes and to simulate them.

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Technology & Engineering