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Investigation on Sige Selective Epitaxy for Source and Drain Engineering in 22 NM CMOS Technology Node and Beyond

Investigation on Sige Selective Epitaxy for Source and Drain Engineering in 22 NM CMOS Technology Node and Beyond

Paperback

Series: Springer Theses

Technology & EngineeringPhysics

ISBN10: 9811500487
ISBN13: 9789811500480
Publisher: Springer
Published: Oct 2 2020
Pages: 115
Weight: 0.43
Height: 0.28 Width: 6.14 Depth: 9.21
Language: English
This thesis presents the SiGe source and drain (S/D) technology in the context of advanced CMOS, and addresses both device processing and epitaxy modelling.
As the CMOS technology roadmap calls for continuously downscaling traditional transistor structures, controlling the parasitic effects of transistors, e.g. short channel effect, parasitic resistances and capacitances is becoming increasingly difficult. The emergence of these problems sparked a technological revolution, where a transition from planar to three-dimensional (3D) transistor design occurred in the 22nm technology node.

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