• Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Interconnect and Temperature Aware Unified Physical and High Level Synthesis

Interconnect and Temperature Aware Unified Physical and High Level Synthesis

Hardcover

Technology & EngineeringGeneral Computers

ISBN10: 9400718926
ISBN13: 9789400718920
Publisher: Springer Nature
Published: Nov 12 2025
Pages: 250
Language: English

The exponential scaling in CMOS transistor sizes over the past three decades have enabled spectacular advances in integrated circuit technology, allowing the integration of more than a billion transistors in modern very large-scale integrated (VLSI) circuits. Over the last four decades, transistor scaling has followed Moore's law, and according to projections made by the International Technology Roadmap for Semiconductors (ITRS), minimum feature sizes are expected to reach 22nm by 2012. The primary drivers for transistor scaling are the associated benefits of lower system costs, improved performance, and system reliability.

Also in

Technology & Engineering