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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Integrated Circuit Defect-Sensitivity: Theory and Computational Models

Integrated Circuit Defect-Sensitivity: Theory and Computational Models

Pineda de Gyvez, José

Hardcover

Series: The Springer International Engineering and Computer Science, Book 208

Technology & Engineering

ISBN10: 0792393066
ISBN13: 9780792393061
Publisher: Springer Nature
Published: Dec 31 1992
Pages: 167
Weight: 1.00
Height: 0.50 Width: 6.14 Depth: 9.21
Language: English
The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the silicon foundry concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders.

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