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Embedded System Design: Modeling, Synthesis and Verification

Embedded System Design: Modeling, Synthesis and Verification

Hardcover

Technology & EngineeringGeneral ComputersProgramming

ISBN10: 1441905030
ISBN13: 9781441905031
Publisher: Springer Nature
Published: Aug 24 2009
Pages: 352
Weight: 1.56
Height: 0.88 Width: 6.14 Depth: 9.21
Language: English

Embedded System Design: Modeling, Synthesis and Verification introduces a model-based approach to system level design. It presents modeling techniques for both computation and communication at different levels of abstraction, such as specification, transaction level and cycle-accurate level. It discusses synthesis methods for system level architectures, embedded software and hardware components. Using these methods, designers can develop applications with high level models, which are automatically translatable to low level implementations. This book, furthermore, describes simulation-based and formal verification methods that are essential for achieving design confidence. The book concludes with an overview of existing tools along with a design case study outlining the practice of embedded system design. Specifically, this book addresses the following topics in detail:

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