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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Design and Implementation of 5G algorithms on SIMD vector processor

Design and Implementation of 5G algorithms on SIMD vector processor

Guo Jiabing

Paperback

Technology & Engineering

ISBN10: 365974588X
ISBN13: 9783659745881
Publisher: Lap Lambert Academic Pub
Published: Jun 30 2015
Pages: 100
Weight: 0.35
Height: 0.24 Width: 6.00 Depth: 9.00
Language: English
With the wide spread of wireless technology, the time for 4G has arrived, and 5G will appear not so far in the future. However, no matter whether it is 4G or 5G, low latency is a mandatory requirement for baseband processing at base stations for modern cellular standards. In particular, in a future 5G wireless system, with massive MIMO and ultra-dense cells, the demand for low round trip latency between the mobile device and the base station requires a baseband processing delay of 1 ms. This is 10 percentage of today's LTE-A round trip latency, while at the same time massive MIMO requires large-scale matrix computations. This is especially true for channel estimation and MIMO detection at the base station. Therefore, it is essential to ensure low latency for the user data traffic. In this master's thesis, LTE/LTE-A uplink physical layer processing: channel estimation/MIMO detection are examined. The key aspect which affects the algorithms' speed is identified as the need for massive complex matrix inversion. A parallel coding scheme is proposed to implement a matrix inversion kernel algorithm on a single instruction multiple data stream (SIMD) vector processor.

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