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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Digital CMOS Circuit Design

Digital CMOS Circuit Design

Annaratone, Silvia

Paperback

Series: The Springer International Engineering and Computer Science, Book 16

Technology & Engineering

ISBN10: 1461294096
ISBN13: 9781461294092
Publisher: Springer Nature
Published: Oct 1 2011
Pages: 384
Weight: 1.19
Height: 0.80 Width: 6.14 Depth: 9.21
Language: English
In light of decreasing feature size and greater sophistication of modern processing technology, CMOS has become increasingly attractive, pro- viding low-power (at moderate frequencies), good scalability, and rail-to- rail operation. For many designers, particularly those approaching VLSI from a system viewpoint, previous experience has been mainly with ratioed NMOS design, and so there is a need to buildon this experienceand make a naturaltransition into CMOS design. Indeed, there ismuch that can bebor- rowed from NMOS experience, mainly centered around the techniques for creating N channel pulldown structures. Based on these contributions, CMOS has now grown to the point where there are several circuit styles which have evolved, and these are amply described in this book. Starting at the level ofthe individual MOSFET, basic building blocks are described, as well as the variety of CMOS fabrication processes in contemporary usage. Circuit style issues are then expandedto providethe user with several useful design methodologies, andmuchcareisgiventoelectricalperformancecon- siderations, including characteristics of interconnect, gate delay, and I/O buffering. This understanding is then applied to macro-sized components, including array multipliers, where the reader acquires a unified view of ar- chitectural performance through parallelism, and circuit performance through scrupulousattentionto device sizingandcontrolofparasiticcircuit elements. In addition, layout techniques to avoid latchup, a consideration not previously encountered by NMOS designers, are given careful treatment.

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