Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Designing Reliable and Efficient Networks on Chips

Designing Reliable and Efficient Networks on Chips

Murali, Srinivasan

Hardcover

Series: Lecture Notes in Electrical Engineering, Book 34

Technology & EngineeringGeneral Computers

ISBN10: 1402097565
ISBN13: 9781402097560
Publisher: Springer Nature
Published: Apr 21 2009
Pages: 198
Weight: 1.05
Height: 0.50 Width: 6.14 Depth: 9.21
Language: English
Preface. 1 Introduction. 1.1 Networks on Chips: Scalable interconnects for SoCs. 1.2 NoC Design Challenges. 1.3 Book Overview. 1.4 Related Work. Part I NoC Design Methods 2 Designing Crossbar Based Systems. 2.1 Problem Motivation and Application Traffic Analysis. 2.2 Design Methodology. 2.3 Exact Approach to Crossbar Synthesis. 2.4 Heuristic Approach to Crossbar Synthesis. 2.5 Experiments and Case Studies. 2.6 Summary. 3 Netchip Tool Flow For NoC Design. 3.1 Front-End Design Phase. 3.2 Architectural Design Phase: The xpipes NoC Library. 3.3 Summary. 4 Designing Standard Topologies. 4.1 On-Chip Traffic Modeling. 4.2 Problem Formulation. 4.3 Mapping and Physical Planning Algorithm. 4.4 Physical Planning. 4.5 Experiments and Case Studies. 4.6 Summary. 5 Designing Custom Topologies. 5.1 Objectives. 5.2 Input Models. 5.3 Design Algorithms. 5.4 Experiments and Case Studies. 5.5 Summary. 6 Supporting Multiple Applications. 6.1 The Aethereal NoC Architecture. 6.2 Design Methodology. 6.3 Use-Case Pre-Processing. 6.4 Unified Mapping-NoC Configuration. 6.5 Simulation Results. 6.6 Summary. 7 Supporting Dynamic Application Patterns. 7.1 NoC Design Challenges for CMPs. 7.2 Basics of the Synthesis Approach. 7.3 Design Flow. 7.4 Problem Formulation. 7.5 Synthesis Algorithm. 7.6 Experimental Results. 7.7 Summary. Part II NoC Reliability Mechanisms 8 Timing-Error Tolerant NoC Design. 8.1 The Double Sampling Technique. 8.2 Using Links as a Storage Medium. 8.3 T-error Link Designs. 8.4 Aggressive Switch/NI Design. 8.5 Dynamic Configuration of the NoC. 8.6 Experimental Results. 8.7 Summary. 9 Analysis of NoC Error Recovery Schemes. 9.1 Switch Architecture Design. 9.2 Energy Estimation and Models. 9.3 Experiments and Simulation Results. 9.4 Summary. 10 Fault-Tolerant Route Generation. 10.1 Multi-Path Routing with In-Order Delivery. 10.2 Path Selection Algorithm. 10.3 Multi-path Traffic Splitting. 10.4 Fault-Tolerance Support with Multi-path Routing. 10.5 Simulation Results. 10.6 Summary. 11 NoC Support for Reliable On-Chip Memories. 11.1 Analysis of Multimedia Software. 11.2 Baseline SoC Architecture and Extensions. 11.3 Run-time Fault Tolerant Schemes. 11.4 Experimental Results. 11.5 Summary. 12 Conclusions and Future Directions. 12.1 Putting it All Together. Bibliography.

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