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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Characterization of Hardening by Design Techniques on Commercial, Small Feature Sized Field-Programmable Gate Arrays

Characterization of Hardening by Design Techniques on Commercial, Small Feature Sized Field-Programmable Gate Arrays

Simmons, Thomas E.

Paperback

Technology & Engineering

ISBN10: 1288255462
ISBN13: 9781288255467
Publisher: Biblioscholar
Published: Nov 9 2012
Pages: 70
Weight: 0.24
Height: 0.15 Width: 6.14 Depth: 9.21
Language: English

This thesis experimentally tests and evaluates programmable logic devices under gamma irradiation to determine radiation effects and characterize improvements of various hardening by design techniques - Error Correction Coding(ECC) and Triple Modular Redundancy (TMR). The TMR circuit includes three different functional implementations of adders compared to TMR voted circuits of those same adders. The TMR is implemented with the same functional adders and as a Functional TMR (FTMR) with three different function adders that are voted on. These adders are connected to single voter TMR and FTMR circuits to evaluate the improvements. The circuit is designed to check for errors in memory data, stuck bit values in the memory, and the performance improvements that ECC provides the system. The results show that TMR or FTMR circuits failed at a rate at or above the single copy adders. This results from the single point of failure created by the voting logic in the radiation environment. When the TMR or FTMR circuit is moved off-chip, the TMR single point of failure is removed and the results demonstrate much lower SEU error rates.

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