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Characterization and Design of High Level VHDL I/Q Frequency Downconverter via Special Sampling Scheme
Paperback
Technology & EngineeringGeneral Computers
ISBN13: 9781025118468
Publisher: Hutson Street Press
Published: May 22 2025
Pages: 222
Weight: 0.70
Height: 0.47 Width: 6.14 Depth: 9.21
Language: English
This study explores the characterization and implementation of a Special Sampling Scheme (SSS) for In-Phase and Quad-Phase (I/Q) downconversion utilizing top-level, portable design strategies. The SSS is an under-developed signal sampling methodology that can be used with military and industry receiver systems, specifically, United States Air Force (USAF) video receiver systems. The SSS processes a digital input signal-stream sampled at a specified sampling frequency, and downconverts it into In-Phase (I) and Quad-Phase (Q) output signal-streams. Using the theory and application of the SSS, there are three main objectives that will be accomplished: characterization of the effects of input, output, and filter coefficient parameters on the I/Q imbalances using the SSS; development and verification of abstract, top-level VHDL code of the I/Q SSS for hardware implementation; and finally, development, verification, and analysis of variation between synthesizable pipelined and sequential VHDL implementations of the SSS for Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC).
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Characterization and Design of High Level VHDL I/Q Frequency Downconverter via Special Sampling Scheme
Somann, Jesse P.
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Somann, Jesse P.
Characterization and Design of High Level VHDL I/Q Frequency Downconverter via Special Sampling Scheme
Somann, Jesse P.
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