Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Analysis of DRAM Cell Designs for Nanometer-Scale Memories

Analysis of DRAM Cell Designs for Nanometer-Scale Memories

Asthana, Prateek

Paperback

Business General

ISBN10: 6202557400
ISBN13: 9786202557405
Publisher: Lap Lambert Academic Pub
Published: May 20 2020
Pages: 80
Weight: 0.28
Height: 0.19 Width: 6.00 Depth: 9.00
Language: English
This book is aimed at improving the power consumption and timing parameter for Dynamic Random Access Memory cells which are used in the construction of the main memory cell. DRAM is widely used for main memories in personal and mainframe computers and engineering workstations. DRAM memory cell is used for reading and write operation for single bit storage for circuits. A single DRAM cell is capable of storing 1bit data in the capacitor in the form of charge. In this book, three different DRAM memory cells are constructed on TANNER EDA, their simulation is carried out. Average power consumption, read access time, write access time and retention time values are calculated for all the three SDRAM cells. The three DRAM cells used are 4T, 3T, and 3T1D DRAM memory cells. Average power consumption, read access time, write access time and retention time-values are calculated at varying supply voltages. To improve the average power consumption, read access time, write access time, and retention time of the 3T1D DRAM memory cell techniques are applied. After the application of techniques on the circuit design, all the parameter values are again calculated and compared with existing value.

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