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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Analysis and Design of Networks-On-Chip Under High Process Variation

Analysis and Design of Networks-On-Chip Under High Process Variation

Ezz-Eldin, Rabab
El-Moursy, Magdy Ali
Hamed, Hesham F. a.

Paperback

Technology & EngineeringGeneral Computers

ISBN10: 3319798375
ISBN13: 9783319798370
Publisher: Springer Nature
Published: Mar 23 2019
Pages: 141
Weight: 0.53
Height: 0.35 Width: 6.14 Depth: 9.21
Language: English

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

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