Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
612-822-4611

  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Low Power High Speed Fully Differential Double Tail Dynamic Voltage Comparator

Low Power High Speed Fully Differential Double Tail Dynamic Voltage Comparator

Krishan Mehra

Paperback

General Reference

ISBN10: 1685090214
ISBN13: 9781685090210
Publisher: Notion Press
Published: Mar 16 2026
Pages: 64
Weight: 0.49
Height: 0.17 Width: 8.50 Depth: 11.00
Language: English

Nowadays a low power, high speed, and small size ADCs are the essential candidates for every electronics circuit to interface the analog domain to the digital domain. An analog to digital consists of numbers of comparator blocks. So, the designing of high-speed analog to digital converter, it becomes necessary to use low power high-speed dynamic comparators for high speed of analog to digital converter (ADC). Existing comparators need a high accuracy clock and extreme drive current and also requires a large amount of power. These requirements make the comparator design more crucial and cost-effective. There are many comparator circuits are suggested in the literature to maintain the speed and power of the comparator, and to overcome the disadvantages of existing comparators. A dynamic comparator is a good candidate for high-speed ADCs. But there is a trade-off between speed and offset voltage. A dynamic comparator comprises a cross-coupled latch circuit and a differential amplifier circuit. Various mismatches exist in dynamic comparators such as threshold mismatch and transconductance mismatch. These mismatches will lead to increase offset voltage and also affects the resolution of the comparator.

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