Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip

High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip

Wang, Zheng
Chattopadhyay, Anupam

Paperback

Series: Computer Architecture and Design Methodologies

Technology & EngineeringGeneral Computers

ISBN10: 9811093210
ISBN13: 9789811093210
Publisher: Springer Nature
Published: May 12 2018
Pages: 197
Weight: 0.69
Height: 0.46 Width: 6.14 Depth: 9.21
Language: English
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

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