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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS

Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS

Noia, Brandon
Chakrabarty, Krishnendu

Hardcover

Technology & EngineeringGeneral Computers

ISBN10: 3319023772
ISBN13: 9783319023779
Publisher: Springer Nature
Published: Dec 2 2013
Pages: 245
Weight: 1.45
Height: 0.80 Width: 6.00 Depth: 9.20
Language: English
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

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