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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Formal Semantics and Proof Techniques for Optimizing VHDL Models

Formal Semantics and Proof Techniques for Optimizing VHDL Models

Umamageswaran, Kothanda
Pandey, Sheetanshu L.
Wilsey, Philip A.

Hardcover

Technology & EngineeringGeneral MathematicsProgramming

ISBN10: 0792383753
ISBN13: 9780792383758
Publisher: Springer Nature
Published: Nov 30 1998
Pages: 158
Weight: 0.96
Height: 0.50 Width: 6.14 Depth: 9.21
Language: English
Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

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