Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
A Single Chip Low Power Implementation of an Asynchronous FFT Algorithm for Space Applications

A Single Chip Low Power Implementation of an Asynchronous FFT Algorithm for Space Applications

Hunt, Bruce W.

Paperback

Technology & EngineeringGeneral Education

ISBN10: 1249584248
ISBN13: 9781249584247
Publisher: Biblioscholar
Published: Oct 3 2012
Pages: 130
Weight: 0.42
Height: 0.28 Width: 6.14 Depth: 9.21
Language: English

A fully asynchronous fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifically for a low power implementation. The novelty of this architecture lies in its high localization of components and pipelining with no need to share a global memory. High throughput is attained using large numbers of small, local components working in parallel. A derivation of the algorithm from the discrete Fourier transform is presented followed bya discussion of circuit design parameters; specifically, those relevant to space applications. The generic architecture is explained with a survey of the 16-point FFT architecture specific to this project. An implementation, which included a test chip fabricated through MOSIS, is described. Finally, simulation results based on layout extractions are presented and an outline for future work is given.

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