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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Wafer-Level Integrated Systems: Implementation Issues

Wafer-Level Integrated Systems: Implementation Issues

Tewksbury, Stuart K.

Paperback

Series: The Springer International Engineering and Computer Science, Book 70

Technology & EngineeringGeneral Gardening

ISBN10: 1461288983
ISBN13: 9781461288985
Publisher: Springer Nature
Published: Feb 9 2012
Pages: 456
Weight: 1.46
Height: 0.96 Width: 6.14 Depth: 9.21
Language: English
From the perspective of complex systems, conventional Ie's can be regarded as discrete devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys- tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term wafer- level is perhaps more appropriate than wafer-scale. A wafer-level monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, wafer-scale merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.

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