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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Digital System Test and Testable Design: Using Hdl Models and Architectures

Digital System Test and Testable Design: Using Hdl Models and Architectures

Navabi, Zainalabedin

Paperback

PhilosophyTechnology & EngineeringGeneral Mathematics

ISBN10: 1489979271
ISBN13: 9781489979278
Publisher: Springer Nature
Published: Aug 23 2016
Pages: 435
Weight: 1.74
Height: 0.93 Width: 7.00 Depth: 10.00
Language: English
Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods

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