• Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Verilog Coding for Logic Synthesis

Verilog Coding for Logic Synthesis

Hardcover

Technology & EngineeringGeneral Computers

ISBN10: 0471429767
ISBN13: 9780471429760
Publisher: Wiley-Interscience
Published: Apr 17 2003
Pages: 336
Weight: 1.31
Height: 0.85 Width: 6.40 Depth: 9.40
Language: English
Provides a practical approach to Verilog design and problem solving.
* Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
* Includes over 90 design examples.
* There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.
* Book is suitable for use as a textbook in EE departments that have VLSI courses

Also in

General Computers