Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
System-On-Chip Test Architectures: Nanometer Design for Testability Volume .

System-On-Chip Test Architectures: Nanometer Design for Testability Volume .

Stroud, Charles E.
Wang, Laung-Terng
Touba, Nur A.

Hardcover

Series: Systems on Silicon

Technology & EngineeringGeneral Computers

ISBN10: 012373973X
ISBN13: 9780123739735
Publisher: Morgan Kaufmann Publ Inc
Published: Nov 1 2007
Pages: 896
Weight: 3.48
Height: 1.60 Width: 7.66 Depth: 9.25
Language: English
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

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