Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
612-822-4611

  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
RISC-V on RISC-V: Programming and Modeling

RISC-V on RISC-V: Programming and Modeling

Bakowski, Przemyslaw

Paperback

General Computers

ISBN13: 9798257936715
Publisher: Independently Published
Published: Apr 18 2026
Pages: 158
Weight: 0.65
Height: 0.34 Width: 7.44 Depth: 9.69
Language: English
This book presents a complete didactic and development platform to teach and model the RISC-V instruction set architecture (ISA) through a hands-on and integrated approach. Instead of separating software and hardware, it combines both into a unified learning framework.

The method is two-fold, combining programming and hardware modeling, and also self-contained: RISC-V systems are studied and simulated using a RISC-V platform itself. This modeling RISC-V on RISC-V approach allows learners to directly connect assembly code, binary execution, and hardware behavior.

The platform is designed to be accessible and affordable (around 100 USD or euros) and relies entirely on open-source tools, including compilers, simulators, and waveform viewers. It is therefore suitable for students, educators, and individual learners.

The content is organized into Programming Labs (PLabs) and Modeling Labs (MLabs), providing a progressive path from basic programming to architectural design.

The PLabs introduce RISC-V assembly through simple examples involving arithmetic operations, registers, and input/output. Learners explore instruction encoding using debugging tools, examining binary formats and manually constructing machine code. This strengthens the link between assembly and low-level representation.

The MLabs introduce Verilog HDL and processor modeling. Students begin with a simplified RV32I implementation focusing on R-type instructions, then progressively extend the design to a more complete architecture, including additional instructions and the M extension.

A key aspect is the interaction between software and hardware. Programs developed in the PLabs are compiled into binaries and injected into the Verilog models. Simulation and waveform analysis allow learners to observe instruction execution at the hardware level, from fetch to execution.

Because the workflow runs entirely on a RISC-V platform, it forms a coherent and closed ecosystem that supports iterative experimentation. Users can modify both software and hardware and immediately observe the results.

The platform is also open and extensible, enabling further exploration of RISC-V programming, processor design, and system-level experimentation. It provides a strong practical foundation for understanding modern open processor architectures.

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