Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
612-822-4611

  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Prefetch Input Queue

Prefetch Input Queue

Surhone, Lambert M.
Tennoe, Mariam T.
Henssonow, Susan F.

Paperback

General Computers

Currently unavailable to order

ISBN10: 6132996125
ISBN13: 9786132996121
Publisher: Vdm Verlag Dr Mller Ag & Co Kg
Pages: 98
Weight: 0.34
Height: 0.23 Width: 9.02 Depth: 6.00
Language: English
High Quality Content by WIKIPEDIA articles! Most modern processors load their instructions some clock cycles before they execute them. This is achieved by pre-loading machine code from memory into a prefetch input queue (PIQ). This behavior only applies to von Neumann computers (that is, not Harvard architecture computers) that can run self-modifying code and have some sort of instruction pipelining. Nearly all computers fulfill these three requirements. Usually, the prefetching behavior of the PIQ is invisible to the programming model of the CPU. However, there are some circumstances where the behavior of PIQ is visible, and needs to be taken into account by the programmer. When the x86-processor changes mode from realmode to protected mode and vice versa, the PIQ has to be flushed, or else the CPU will continue to translate the machine code as if it were written in its last mode. If the PIQ is not flushed, the processor might translate its codes wrong and generate an invalid instruction exception.

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