Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
612-822-4611

  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Logic Synthesis for Finite State Machines Based on Linear Chains of States: Foundations, Recent Developments and Challenges

Logic Synthesis for Finite State Machines Based on Linear Chains of States: Foundations, Recent Developments and Challenges

Barkalov, Alexander
Titarenko, Larysa
Bieganowski, Jacek

Hardcover

Series: Studies in Systems, Decision and Control, Book 113

Technology & EngineeringGeneral Computers

ISBN10: 3319598368
ISBN13: 9783319598369
Publisher: Springer Nature
Published: Jul 6 2017
Pages: 225
Weight: 1.12
Height: 0.56 Width: 6.14 Depth: 9.21
Language: English

This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation.

1 different editions

Also available

Also in

General Computers

View All