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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Fully-Depleted Soi CMOS Circuits and Technology for Ultralow-Power Applications

Fully-Depleted Soi CMOS Circuits and Technology for Ultralow-Power Applications

Sakurai, Takayasu
Matsuzawa, Akira
Douseki, Takakuni

Hardcover

Technology & EngineeringGeneral Computers

ISBN10: 0387292179
ISBN13: 9780387292175
Publisher: Springer Nature
Published: Apr 11 2006
Pages: 411
Weight: 2.00
Height: 0.90 Width: 6.40 Depth: 9.74
Language: English

The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society. Fully-depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V. The topics include the minimum required knowledge of the fabrication of SOI substrates; FD-SOI devices and the latest developments in device and process technologies; and ultralow-voltage circuits, such as digital circuits, analog/RF circuits, and DC-DC converters. Each ultra-low-power technique related to devices and circuits is fully explained using figures to help understanding.

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