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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Fault and Defect Tolerant Computer Architectures

Fault and Defect Tolerant Computer Architectures

Roelke, George R.

Hardcover

Technology & EngineeringGeneral Computers

ISBN10: 1025140540
ISBN13: 9781025140544
Publisher: Hutson Street Press
Published: May 22 2025
Pages: 422
Weight: 1.69
Height: 0.94 Width: 6.14 Depth: 9.21
Language: English

As conventional silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology continues to shrink, logic circuits are increasingly subject to errors in- duced by electrical noise and cosmic radiation. In addition, the smaller devices are more likely to degrade and fail in operation. In the long term, new device technolo- gies such as quantum cellular automata and molecular crossbars may replace silicon CMOS, but they have significant reliability problems. Rather than requiring the cir- cuit to be defect-free, fault tolerance techniques incorporated into an architecture allow continued system operation in the presence of faulty components. This research addresses construction of a reliable computer from unreliable de- vice technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied, and the yield of the system is modelled. Yield and hardware cost models are developed for the fault tolerance techniques used in the architecture. Fault and defect tolerant designs are created for the processor, and its most critical component, the cache memory.

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