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CMOS VLSI Layout and Verification of a SIMD Computer

CMOS VLSI Layout and Verification of a SIMD Computer

Paperback

Technology & EngineeringGeneral Computers

ISBN10: 1025156412
ISBN13: 9781025156415
Publisher: Hutson Street Press
Published: May 22 2025
Pages: 76
Weight: 0.26
Height: 0.16 Width: 6.14 Depth: 9.21
Language: English

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

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