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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications

Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications

Shacham-Diamand, Yosi
Datta, Madhav
Osaka, Tetsuya

Paperback

Technology & EngineeringChemistry

ISBN10: 1461497442
ISBN13: 9781461497448
Publisher: Springer Nature
Published: Nov 28 2014
Pages: 552
Weight: 1.74
Height: 1.16 Width: 6.14 Depth: 9.21
Language: English
In Advanced ULSI interconnects - fundamentals and applications we bring a comprehensive description of copper-based interconnect technology for ultra-lar- scale integration (ULSI) technology for integrated circuit (IC) application. In- grated circuit technology is the base for all modern electronics systems. You can ?nd electronics systems today everywhere: from toys and home appliances to a- planes and space shuttles. Electronics systems form the hardware that together with software are the bases of the modern information society. The rapid growth and vast exploitation of modern electronics system create a strong demand for new and improved electronic circuits as demonstrated by the amazing progress in the ?eld of ULSI technology. This progress is well described by the famous Moore's law which states, in its most general form, that all the metrics that describe integrated circuit performance (e. g., speed, number of devices, chip area) improve expon- tially as a function of time. For example, the number of components per chip d- bles every 18 months and the critical dimension on a chip has shrunk by 50% every 2 years on average in the last 30 years. This rapid growth in integrated circuits te- nology results in highly complex integrated circuits with an increasing number of interconnects on chips and between the chip and its package. The complexity of the interconnect network on chips involves an increasing number of metal lines per interconnect level, more interconnect levels, and at the same time a reduction in the interconnect line critical dimensions.

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