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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
A Framework for Automated Hw/SW Co-Verification of Systemc Designs Using Timed Automata

A Framework for Automated Hw/SW Co-Verification of Systemc Designs Using Timed Automata

Herber, Paula

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General Computers

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ISBN10: 3832525114
ISBN13: 9783832525118
Publisher: Logos Verlag Berlin
Published: Jun 30 2010
Pages: 145
Weight: 0.50
Height: 0.40 Width: 5.68 Depth: 8.04
Language: English
In this dissertation, we present a systematic, comprehensive, and formally founded quality assurance process, which allows automated co-verification of digital hardware/software systems that are modeled in SystemC. The main idea is to apply model checking to verify that an abstract design meets a requirements specification and to generate conformance tests to check whether refined designs conform to this abstract design. As formal foundation, we define a formal semantics of SystemC by a transformation into the well-defined semantics of UPPAAL timed automata. The automatically generated timed automata model can be verified using the UPPAAL model checker and it can be used to generate conformance tests. With that, we obtain guarantees about liveness, safety, and timing properties of the abstract design, which serves as a specification, and we can ensure the consistency of each refined design to that. The result is a HW/SW co-verification flow that supports the HW/SW co-development process continuously from abstract design down to the implementation. The complete verification flow is implemented in our Framework for the Verification of SystemC designs using Timed Automata (VeriSTA) and its applicability and performance are shown by experimental results.

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